Multi-port random access memories (RAM) are faster than standard RAM. They are commonly referred to as video random access memories (VRAM) because of their effectiveness in video systems. One such multi-port memory is described in U.S. Pat. No. 4,891,794 issued to Hush et al., entitled "Three Port Random Access Memory," and assigned to the assignee of the present invention and incorporated herein by reference thereto. In simple form, a VRAM includes a dynamic random access memory (DRAM) and DRAM controller, and a serial access memory (SAM). Each SAM is essentially a long shift register which can receive a block of data from the DRAM and serially shift the data out through a data port. The SAM can also serially shift data in through the serial port and transfer the data to the DRAM.
The DRAM is a dynamic array for storing multi-bit memory registers in multiple two dimensional planes. Each memory register has a memory cell in each plane. The DRAM has column and row address line inputs and a plurality of input/output lines. Each of the cells in a multi-bit memory registers is defined by the same row and column address in the multiple planes. Each SAM has a multi-bit register row associated with each of the planes of the DRAM. The columns of the DRAM correspond to the bits of the SAM register row.
Various features have been incorporated in VRAMs to speed the transfer of data to and from an associated graphics processor or microprocessor. One example of a function used to speed memory writing is the "block write" function. U.S. Pat. No. 5,282,177 issued to McLaury, entitled "Multiple Register Block Write Method and Circuit for Video DRAMs," assigned to the assignee of the present invention and entirely incorporated herein by reference thereto, describes several methods and circuits for block writing to a DRAM.
The block write is useful in a VRAM to quickly clear a large area of frame buffer or to create a background for a display. The block write function simultaneously writes from a write register, which in certain applications be a color register, to a block of adjacent multi-bit memory registers instead of writing to each register individually. The block of multi-bit memory registers can be a preselected number of registers in a row of the DRAM (selective block write function) or the entire row of memory registers (flash block write function). The block of cells of the block of multi-bit memory registers in each plane of memory is written to the same state. That is, one bit of a multi-bit write register is written to each block of cells in a plane.
U.S. Pat. No. 5,282,177 discloses a multiple register block write. The multiple register block write is similar to the block write described above except the write register has multiple registers. The multiple write register has a plurality of eight bit static memory registers. Any one of the plurality of write memory registers can transfer data to the VRAM. The multiple write register, therefore, eliminates the need to re-load a single write register for different block writes by preloading all of the multiple write memory registers.
In order to perform the selective block write function described above, an initial start address, including a row and column address, is latched to address the first memory register of a preselected block of memory registers such that data can then be written simultaneously from one or more write registers to the preselected block of adjacent memory registers. Similarly, in flash block write, an initial row address is latched to address the first memory register of a row of multi-bit memory registers such that data can then be written simultaneously from one or more write registers to the row of memory registers.
However, in selective block write, an externally generated column address is strobed to the DRAM via the address pins for each block write cycle in the row addressed. Such addressing is inefficient when it is desired to perform multiple block writes to adjacent blocks of memory registers.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device that provides for more efficient addressing when it is desired to perform multiple block writes to adjacent blocks of memory registers.